Parity Based Fault Detection Techniques for S-box/ Inv S-box Advanced Encryption System
نویسنده
چکیده
Concurrent fault detection plays a vital role in hardware implementation in order to prevent losing the original message This paper explores the new low-cost fault detection scheme for the S-box/ InvS-box of AES using a parity prediction technique. The predicted block was divided into seven blocks, to compare between the actual parity output and the predicted parity output results in the error indication flag for the corresponding block. The predicted blocks were developed with formulations compatible with the new S-box/ InvS-box simulated using 130nm CMOS technology, in Mentor Graphic environment. This proposed fault detection has achieved the total error coverage of about 99%. The total area implementation for the fault detection predicted parity block of the S-box/ InvS-box required 49 XORs, six XNORs, nine ANDs, one inverter, two ORs and one NAND gate. The proposed fault detection has the low hardware complexities which lead to a low cost and low power design.
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